System for Mapping First in First Out (FIFOs) To Processor Address Space

Linderman; Mark H, Wu; Qing, Fitzgerald; Dennis
Summary
There is need for a more efficient means for microprocessors to handle queued data packets characterized by high data rates. In the fields of computer science and computing system architecture, FIFO is an acronym for "first in, first out," which is a common method for organizing and manipulating a data buffer as a queue. In a FIFO implementation, processing of data structures that are input to a data buffer is analogous to servicing a queue on a first-come, first-served (FCFS) basis. That is, the oldest (first) entry into a FIFO buffer is processed first. Communication network bridges, switches, and routers used in computer networks may employ FIFO buffers to temporarily store data structures (referred to as "data packets") as they await service from limited processing resources that are tasked with facilitating progress of the data packets through a computing architecture. In common computer network architectures, one or more FIFO buffers may be dedicated to service a single network connection. Also, multiple FIFOs may be designed to simultaneously and independently queue different types of information (e.g., data type-specific buffers). Embodiments of the present invention are directed to systems, methods, and devices for high-data rate computation using first in-first out (FIFO) queues and control mechanisms in embedded, microprocessor, and/or multiprocessor computer systems. Embodiments of the present invention may employ a small state machine or microcontroller to advantageously convert a simple FIFO mechanism into a powerful tool to map data into memory, transform data representation, and/or to forward data across a distributed computing architecture. The FIFO abstraction and the mapping into simple processor instructions also may advantageously allow low-power processors to more efficiently manipulate incoming and outgoing data.
Markets
Semiconductors, Integrated Circuit Design, Communications, Computers
IP Status
This technology is the subject of a US patent granted on 2019-12-31. Rights are assigned to the United States Air Force but should be available for licensing.
Key Words
FIFO, Microprocessor, Efficient, Processing
Licensing
Technology is available for licensing through the US Air Force. Contact the Caesar Group to help connect you to the Tech Transfer agent at the responsible Air Force organization.
Published Date
2019-12-31
Funding Agency
Air Fore
References