Prevent Hackers From Using Side Channel Power Attacks To Determine The AES Encryption Key
Weyna; Lisa, Rooks; John W.
Summary
This invention provides an technology for obscuring power consumption of hardware implementation of the AES algorithm. Two distinct methods for accomplishing this are as follows: 1) Simultaneously executing a processor floating point operation while executing the AES algorithm, 2) Circuit layout techniques that negate power analy key hacks. These methods prevent hackers the opportunity to determine the AES key value during a side channel power attack.
Markets
Cyber security, Information Assurance, Integrated Circuit Design and Manufacture
Maturity
Technology has been patented but still needs further validation testing.
IP Status
This technology is the subject of a US patents granted in Sept and Oct 2015. Rights are assigned to the United States Air Force but should be available for licensing.
Key Words
Cyber Security, Cryptography, Hardware Design, power management, Advanced Encryption Standard (AES), AES Encryption
Licensing
Technology is available for licensing through the US Air Force. Contact the Caesar Group to help connect you to the Tech Transfer agent at the responsible Air Force organization.
References
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